writing RTL in veriloga

Discussion in 'Cadence' started by DReynolds, Oct 26, 2006.

  1. DReynolds

    DReynolds Guest

    I am working on a mixed signal chip that is mostly analog and my
    question is about modeling and simulating the digital. Has anyone
    written their RTL in veriloga? If so, what are the pluses and minuses?
    I have modeled counters and such and have not found any problems in
    generating the functionality I need in veriloga but I have not tried
    writing an FSM...

    I realize that with AMS I can run verilog, but most of the time I don't
    have access to the license, so I am looking an alternative.

    David
     
    DReynolds, Oct 26, 2006
    #1
  2. DReynolds

    Andrew Beckett Guest

    Well, you can do it, but it's only really practical for relatively small amounts
    of logic, since you're treating all your logic nets as electrical. You need to
    make sure you model transitions properly in the models to avoid (excessively)
    discontinuous behaviour...

    Andrew.
     
    Andrew Beckett, Nov 14, 2006
    #2
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