Hello everyone I am having some problems simulating a design. I am using the ams plug in in the hierarchy editor. This is what i did so far: 1.create designs in schematic test them and put them in a schematic file called test. 2.Create a verilog file that outputs the inputs for the designs, created symbol for it and placed it in the test file and connected it. 3.Create a hierarchy editor set it up and all 4.places voltage sources etc in the file now when i run the simulator and get simvision, the signals give me a no value for all the design, including the voltage sources except that verilog file, where i get a value for its outputs. Does anyone know why this is happening? Am i missing a setup value somewhere? Did i miss something? Thank you in advance DJ
