Wired net name in post-layout netlist

Hi Guys,

The layout is extracted with Assura. Then I ran a post-layout
simulation with a config view, in which the av_extracted view is
instantiated instead of schematic vew. However, the net names in
schematic has not one to one map in the av_extracted view because it
is extracted with distributed RC mode. The net is cut into dozens of
segments with wired net names. For example, the net name I111_n13
becomes a few nodes like _29:\I111_n13.

When I tried to plot/save the net voltage in ADE, it failed to find
the net unfortunately.

Open ADE, choose outputs -> Output Setup, fill in Expression I5/
_29:\I111_n13. It becomes (I5/_29 : \I113_n13) automatically.

I think there must be something wrong. Any comments are appreciated.

Best Regards,
Yawei

 

Yawei Guo wrote, on 08/09/09 10:01:

As I said in my posting on the Designer's Guide, the syntax is wrong. Best way
to find out is to select the node on the extracted view. For example, I just did
this and got:

/I1/17:SIDDQb

The hierarchy delimiter will be "/", and there should be no backslash. You're
probably looking at netlist names.

I did this by doing Outputs->To Be Saved (or Plotted).

If you do Outputs->Setup, you can't just type in a hierarchical name. It needs
to be an expression, so would be something like:

v("/I1/17:SIDDQb" ?result 'tran)

or

VT("/I1/17:SIDDQb")

Regards,

Andrew.