Will there be a kit flow paper in the upcoming CDNLive in September?

I haven't been to the users groups in a while but I loved the yearly flow
papers that Cadence flow teams used to give each year detailing their
progress building chips and kits and flows and methodologies for us.

These flows are when Cadence documents how they build a chip using their
tools and then tapes out that chip and tests it to ensure it works, just
like we do every day. Some of the future topics I see are documentation on
building the PDK and on mixing analog and rf with digital on a single chip
in different processes. They were on OpenAccess 2.0 years ago in the paper
that I read but I'm sure they're on the latest OA by now.

The great thing in the last paper I watched was when they stood there and
unabashadly said they filed thousands of change requests each time they
built a chip as their goal wasn't the chip per se but the software working
for us. They got it! They even did this all in the TSMC process (180 I
think if I remember correctly). The last paper I saw said the San Jose
team's chips were on a shuttle waiting for the results to come back to
their lab in Jackson Mississippi.

Anyone know if that flow effort is still ongoing and if the results will be
reported at CDNLive this September? I'd love to have a working flow out of
the box in the TSMC 65 OpenAccess process.

bkp

 

Not sure what will be presented at CDNLive but if your interested in
the TSMC65 Kit then this artical may be of interest.

http://biz.yahoo.com/iw/070626/0270894.html

 

Hey does this mean I can finally just down load from the foundry and
Cadence an entire chip design and models and flow and software that works
out of the boxes? Do any other foundries have this yet?

And what will happen to my huge CAD group who spends most of their times
developing our methodology and flows out of tools that were never built or
tested together and which breaks with every new release of any component in
the flow. Should my CAD department at least start with this and teach with
this and debug with this tsmc thing?

Is this Cadence TSMC 65 kit thing a new dimension in circuit design?
Who built it? Cadence or the foundry? Or did they buy it from one of us
already working? Do they test it so every thing that changes won't break
our flow if we use it?

jim

 

But I think you will have to pay for it.

Do you happen to use *any* other tool in the chain not coming from
Cadence? Then you will still need the CAD group.

They have offered Kits for some time with a generic PDK to show the
users how to use Cadence tools to do designs. These designs have
mostly been of quite practical relevance, maybe bought from someboby
or designed by VCAD for this purpose.

Some people, me included, sees these kits as a result of the fairly
high complexity when dealing with Cadence tools, which lead to a huge
effort in support for Cadence when users start to think for
themselves.

 

Well, Tower is not on my list of vendors, pity. Hope it provides
customer added value so that other foundries will follow.

 

H Svenn,

I was a co-author of that paper at CDNLive last year (also delivered
by Tower at EMEA).

Mutual Tower/Cadence Customers said they shaved MONTHS off their
schedule using this flow.
One, in particular, mentioned in the paper by name, said they saved 9
months in developing a second-source flow to TSMC.

While the design was never the important point (the point was always
to have a fully documented and working flow), the design used to test
the flow was the Eaglet garage-door opener (often used in university
flows) because it contains a small block of the major disciplines. The
original eaglet stressed the flow because it contained full schematic,
layout, simulation, extraction, and parasitic resimulation views for
the combined chip which included an RF LNA & mixer, an analog op amp,
a mixed-signal PLL and ADC, and a digital DSP where the FFT utilized
RAM & ROM memory controlled by the DMA block). Eaglet was, in essence,
a little bit of everything, combined with a complete document that
outlined every single step of the flow, from start to finish.
Thousands of product change requests were filed and fixed for this one
design so that you, the consumer, would not have to find or file these
bugs or enhancements necessary to run the complete flow.

In addition, anyone could reproduce that complete documented &
supported RF/Analog/Mixed-Signal/Digital/Memory/IO flow in a single
day (assuming all the software were prior installed). That's quick-
start value in and of itself.

This Eaglet chip was (AFAIK), the only available design built and
tested and fabricated and supplied to Customers as a foundry reference
chip, at the time it was built years ago. As such, it was ground
breaking for the industry as a whole and for the university community
at large (as it was supplied to them as their classroom laboratory
design of choice at the time via the Cadence Repository for Electronic
Transfer & Exchange http://crete.cadence.com external web site).

As you noted, it is great that the other foundries are taking note and
following suit (more has been created since the groundbreaking Eaglet
was released years ago).

IMHO, all users will benefit from this and similar efforts at other
foundries.

As always, good luck in all that we do to raise capabilities,
John Gianni

 

As you noted, CRETE was pulled a while back (that's why I used the
past tense).

I haven't been involved in the university setting for a while so I'm
not the one who knows.
Maybe folks on the university side can pitch in (e.g., the wonderful
folks over at NCSU and elsewhere doing full flows in a university
setting) ...

On the commercial side, there is a Tower-based flow (as noted); there
are the TSMC "reference flows"; and I saw a recent announcement
regarding Jazz (http://biz.yahoo.com/iw/070723/0280364.html) .... and
I'm sure many more ... I'm just not the one to ask.

Good luck ... I hope some of our university friends pitch in with
further information,
John Gianni