why SE KEEPS telling me that I don't have clock net?

Dear all,

I think I have the clock input in my design, why SE keeps give me
warning that I don't have clock net?

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15:58:47 * PLACE :
15:58:47 * PLACE : Begin LEF/DEF in ...
15:58:47 * PLACE : Reading "dbs/fir_srg.opt.lef" ...
15:58:51 * PLACE : Reading "dbs/fir_srg.opt.def" ...
** SE-USER-60 WARNING ** <------------ SEE HERE
15:58:53 * PLACE : design has no clock net
15:58:53 * PLACE : A total of 1 warning.
15:58:53 * PLACE : Read in 11 layers, 4 routing layers, 0 overlap
layer
15:58:53 * PLACE : Read in 132 macros, 18 used
15:58:53 * PLACE : Read in 414 components
15:58:53 * PLACE : 414 core components: 414 unplaced, 0 placed, 0
fixed
15:58:53 * PLACE : Read in 17 physical pins
15:58:53 * PLACE : 17 physical pins: 0 unplaced, 17 placed, 0 fixed
15:58:53 * PLACE : Read in 2 logical pins
15:58:53 * PLACE : Read in 429 nets
15:58:53 * PLACE : Read in 3 special nets
15:58:53 * PLACE : Read in 2056 terminals
15:58:53 * PLACE : End LEF/DEF in: cpu: 0:00:04, real: 0:00:07, peak:
16.70 megs.

 

You may have clock input in your design but SE doesn't know that as
you don't have any properties on that clock input pin the properties
which tell SE that they are clocks. You usually get these after you do
Clock Tree Generation on your placed DEF.
You can modify your def yourself to add properties like

"PROPERTY CLOCKROOT "PIN clk"

to your clock nets. Then initial placement will pick up these
properties too.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations