Why are those nmos and pmos jumbled when placing cell using SE?

Discussion in 'Cadence' started by Harryzhu, Mar 18, 2005.

  1. Harryzhu

    Harryzhu Guest

    Hi,

    Normally we have nmos and pmos layed regularity so that power and gnd can
    lay easily. But when I place cell using SE5.3, I get those nmos and pmos
    transistor jumbled, why is it? I use the same environment to run another
    project and anything is well. I'm not sure if those files foundry supplied
    to me are wrong or I missed some variable's setting. Ask for your help,
    Thanks a lot!

    Have a good day!

    Best Regards,

    Harryzhu
     
    Harryzhu, Mar 18, 2005
    #1
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