What is the meaning of antenna error in a layout???

Hello,

I am designing a CMOS circuit using AMS CMOS 0.35 (C35B4) library with
the Cadence IC 4.46 software.

I submitted the design to the foundry and it reported me an "antenna"
error. What is the meaning of this error?

When I click on the marker and ask for explanations, I get the following
message:

Location: ("LibraryName" "CircuitName" "Layout")
reason: ANT_MET3_GATE_AR3

Can anyone explain me what is the meaning of this message?

Many thanks for your reply.

Best regards


Lew

 

it's when you have large metal structures connected to the
gate of a mos transistor.

as those are not connected to the bulk, they can collect
large amounts of electric charges during etching, and
eventually cause breakdown of the gate oxide, thus
damaging the transistor.

take a look at http://www.national.com/quality/antenna_ratio_wp.html
for a detailled description.

there are techniques for avoiding antenna effect. for example
jumping to met2 then back to met1 to have a smaller
met1 path connected to the gate.


stephane

 

From the net,


Failure Mechanism
Modern fabrication flows use plasma etching as an integral part of
some process steps. The plasma etching systems create and sustain an
energized and highly ionized state of matter in order to etch or
deposit layers onto silicon wafers. As a result of this exposure,
charges can build up on circuit areas. Ion implant equipment can also
cause charge build up. Uncontrolled discharge of these charges may
cause permanent physical damage to the physical structures on the
device, e.g., transistor gate oxide.

'Antenna' and 'Antenna Ratio'
The propensity for damage to the circuitry on a wafer can be
exacerbated by the existence of 'antenna' structures. The 'antenna' is
an interconnect, i.e., a conductor like polysilicon or metal, that is
not electrically connected to silicon, i.e., not 'grounded', during
the processing steps of the wafer. The connection to silicon would
normally provide an electrical path to bleed-off any accumulated
charges. If the connection to silicon does not exist, charges and may
build up on the interconnect to the point at which rapid discharge
does take place and permanent physical damage results, e.g., to MOSFET
gate oxides. This destructive phenomenon is known as the 'antenna
effect'.

The 'antenna ratio' of an interconnect is used to predict if the
antenna effect will occur. 'Antenna ratio' is defined as the ratio
between the physical area of the conductors making up the antenna to
the total gate oxide area to which the antenna is electrically
connected. A higher ratio implies a greater propensity to fail due to
the antenna effect. This can result either from a relatively larger
area to collect charge or a reduced gate oxide area on which the
charge is concentrated

 

Partha explained it well (I think he is a cad guy). Let me add a few
comments....

Four - five years ago TSMC adds antenna checks on its 0.18 flow.
Newer technologies (0.13, 0.9) certainly have these antenna checks
because they have smaller gate size.

Summary:
- long uniterrupted metal is bad
- bigger diffusion is good
- bigger gate is good

If physical verification (Assura, Calibre) shows the antenna flags,
you need to address them..... If this is custom layout, you need to
fix it manually. If the layout is generated from P&R flow, you need
to modify the flow (Silicon Ensemble, for example, requires antenna
LEF rules, antenna information on standard cells, and turning on a few
SE environment)....

Most foundry will not accept these violations.... You might want to
verify the design before sending them to the foundry.

thanks,
ronald

 

Actually antenna rules have been around since 0.35uM. These types of errors
can render your die inoperable and should be addressed prior to fab. MOSIS
has a good description of the problem here:
http://www.mosis.org/Technical/Designrules/guidelines.html#antenna

ethan