What is the common strategy to do RF simulation and measurement with pads?

Discussion in 'Cadence' started by Frank, Feb 18, 2006.

  1. Frank

    Frank Guest

    Hi all,

    I am designing a integrated CMOS circuit at RF frequency and I am going

    to measure the circuit using wafer probing. I have to add GSG pad
    structures to the RF I/O pins so that I can probe the signal. But these

    pads will introduce additional parasitics that are going to degrade the

    performance (shift the matched frequency, etc) of my circuit.

    Please tell me what the common strategy to deal with this problem.
    Should I match the circuit with the pad to 50 Ohm? Or should I match
    only the circuit (no pad) to 50 Ohm, then put the pad in during layout
    and de-embed the pad's parasitics during measurement?

    Thanks a lot for your help.

    Frank
     
    Frank, Feb 18, 2006
    #1
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