Voltage-scaled digital block simulation with Spectre

Discussion in 'Cadence' started by Taimur, Apr 12, 2010.

  1. Taimur

    Taimur Guest

    Hello all!

    I have a small digital circuit (~200 gates) which is using voltage-
    scaling. It was designed in a 0.35um channel length process with ~0.5
    NMOS and ~0.7 PMOS threshold voltages. However, when trying to
    simulate it with Spectre, the circuit simply doesn't work for deeper
    scaling voltages (<1.3V). I am not absolutely sure, but the block
    should work properly at this range of voltages, and it sounds more
    like a simulation problem than circuit problem. For voltages starting
    at 3.3V to 1.3V, the block works quite fine, but starting at this
    point, the logic simply stucks. Does somebody have a clue?
     
    Taimur, Apr 12, 2010
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. nearest snap to non-uniformly scaled block

  2. Help with warning message from spectre simulation

  3. Threshold voltage equation in Spectre simulator

  4. voltage values for multiple instance voltage sources

  5. How do I measure voltage at trigger signal with MDL?

  6. How to run distributed simulation with spectre?

  7. Problem with spectre noise simulation of multi-rate time-discretesystem

  8. plot Transient voltage of internal BVIC nodes in spectre

Loading...