Visual IP Designer interresting new EDA tool/Automatic VHDL Generation

You kindly invited to visit www.visualipd.com Home of Visual IP
Designer.

You can see flash demo showing the tool in action.
You may also be interrested on getting your free evaluation copy.

Visual IP Designer is an EDA tool for design entry and integration
which enable designers to intuitively build, maintain and reuse their
designs using a full graphical approach. Visual IP Designer provides an
advanced and fast methodology to develop HDL-based designs targeting
ASIC and FPGA. The Visual IP format is able to describe designs at RTL
level in a more flexible and attractive way. The automatic code
generation feature allows obtaining a high quality VHDL code optimized
for synthesis with a non scarified readability.
Because visual representation is closer to human way of thinking,
Visual IP Designer target is to provide a complete range of graphical
means of description replacing the classical textual approach. Unlike
mixed graphical/textual solutions Visual IP Designer allow the
graphical representation at 100% of all the aspects of RTL design.
Visual IP Designer! benefits:
Speed, entring and mainaining a design graphically is faster than usign
multiple vhdl files
Communicating and thinking graphically is more effective than using
text
Dynamic checking, errors are located early during the design entry
phase
High quality generated VHDL code, free of compilation/elaboration
errors, ready for synthesis
Visual IP format may be used for documentation purpose, no need for
redundant documentation
Visual IP allow extended generic capabilities (generic interface,
generic mapping, etc)
Packaging, delivering generic Visual IP format is more attractive and
user freindly than native VHDL files
Reuse interfaces/sub blocks is simple and fast thanks to import/export
capabilities
System integration, assambling Visual IPs is easy, no need for
additional interfaces/parameters description

Cordially

VD author