Virtuoso-XL Placement Planning

Hi all,

I am using virtuoso-XL in IC5.0, with a TSMC 0.25u pdk. In
virtuoso-XL, for a simple gate say 3-i/p AND, The layouts cells are
generated from source , and then the pins are placed on the
PR-boundary edge, and the supply rails already drawn.

On The Placement Planning form, when I look on the components tab, and
calculate, the number of PMOS and NMOS is always zero, Inspite of PMOS
and NMOS being defined in the component types.

Consequently, when i draw a bounding box inside my PR-boundary where i
want my components to be placed, no rows are generated. Also I get a
warning message that power and ground will not be placed.

I have tried a lot of hacks to get around this but do what I will the
palcement rows are not being generated and vcp fails everytime.

Anyone has any ideas?

Also a couple of general questions :
1) Anyone has any idea realistically how does SoC encounter compare
with synopsys's apollo?
2) Any Tips and Tricks for a non-iterative possibly first pass clock
tree generation with CTgen or in SoC Encounter?

Thanks in advance.