Virtuoso Inherited Connections Tutorial (part 1)

Discussion in 'Cadence' started by John Gianni, Sep 27, 2004.

  1. John Gianni

    John Gianni Guest

    Good news.

    SUMMARY:
    Inherited Connections Tutorial (part 1), including layout & physical
    verification & creation of LEF abstracts & DFII abstracts ...

    DETAILS:
    The good news is that part 1 of the new "Virtuoso Inherited
    Connections Flow Guide" (containing a small sample 180nm design &
    design kit with inherited connections) was just released today on
    Sourcelink for Customer use!

    You can pick up the design, design kit, & documented flow at:
    http://sourcelink.cadence.com/docs/files/Tutorials/inheritedconnectiontutorial.html

    Here is the wording at that URL if you're unfamiliar with INHERITED
    CONNECTIONS:

    Inherited connections are an extension to the connectivity model that
    allow you to create signals hierarchically and to override their names
    for selected branches of a design hierarchy. This flexibility allows
    you to design:

    * Parameterized power and ground signals
    * Overridable substrate connections
    * Multiple power supplies for a design

    Download the tutorial database and the "Virtuoso® Inherited
    Connections Flow Guide" manual to learn more about using inherited
    connections with Cadence tools. The manual contains illustrations and
    step-by-step instructions that show how inherited connections let you
    selectively override signals in designs created with the Virtuoso®
    Schematic Editor, and how those connections are available to other
    Cadence tools across the design flow.

    Download the Tutorial on UNIX/Linux (File size: 15MB)

    Coming Soon
    The Virtuoso Inherited Connections Flow Guide manual is a
    work-in-progress.
    We will be extending its depth and breath and plan to cover more of
    the complete design process in the future. Please check this location
    on SourceLink again for the next version, to learn about:

    * The difference between implicit terminals and explicit pins
    * How and when to use implicit terminals versus explicit pins
    * Inherited connections in AMS Designer using supply sensitivity
    * Interaction with the verification environment (ASSURA LVS) or
    with parasitic resimulation

    John Gianni
    Director, Flow Engineering

    Nothing I post to the USENET is company ordered nor sanctioned.
     
    John Gianni, Sep 27, 2004
    #1
  2. That is indeed very good news.
    I just tried out that flow guide and it's absolutely wonderful!

    It only took me a few hours to zip right through its 122 pages and
    simple resistor and inverter based test cases. I'd recommend CAD
    engineers take this freebie from Cadence, if not for the inherited
    connections, then for the flow itself.

    The old "inhconn.tar.Z" tutorial, shipped with the Opus software for
    ages, didn't go any farther than schematic simulation. Since
    everything works with schematics, that wasn't far enough in the flow.

    This new flow tutorial takes the explicit inherited connections
    through layout and farther to the creation of LEF for place and route.
    That's a BIG improvement on the old inhconn tutorial. Thanks Cadence
    flow guys for making it available on Sourcelink.

    I noticed the supplied generic process design kit is a subset of the
    complete GPDK180 available on the crete.cadence.com web site. Also, I
    noticed it has netset properties which Artisan doesn't have. That's
    probably a good idea (for tutorial size & portability reasons) - but
    someone should tell Artisan (ok ARM) that they should add inherited
    connections to their standard cell libraries.

    I also noticed this new inhconn tutorial required the latest versions
    of Opus software. I suspect that's because bugs were fixed in
    inherited connections. I used IC5141 on Linux and it worked fine for
    me. I tried in an older version of IC5033 FCS and I ran into issues.
    So, I guess the recommendations in the document are real. :)

    Thanks for caring about us.
     
    Bonnie Stantini, Sep 28, 2004
    #2
  3. It *is* nice. Well done. About time too.

    We struggled with explicit inherited connections for years before
    realizing implicit is the way to go. This just reinforces our
    decision.

    I just wish Cadence would create these flow tutorials more often.
     
    Wolfgang Franz, Oct 4, 2004
    #3
  4. John Gianni

    Manuel Koch Guest

    Is there any way to acces the documentation without having access to
    sourcelink?
    I work with cadence supplied by europractice and I would really like
    to have that updated tutorial.

    Manuel
     
    Manuel Koch, Oct 8, 2004
    #4
  5. John Gianni

    John Gianni Guest

    Sorry ... I was out on vacation ... just getting through all my emails
    ....
    I'm not sure the best way to get you the tutorial as I am not familiar
    with "europractice". I suggest you contact whomever you normally deal
    with at Cadence and have them contact me or the inherited connections
    task force. (They'll know who I am.)

    Also, for everyone else, it's no longer in the "Whats New" section
    of Sourcelink, so, save this URL for future reference:
    http://sourcelink.cadence.com/docs/files/Tutorials/inheritedconnectiontutorial.html

    Based on Customer input, this is the second-update to the inherited
    connections tutorial, with a tiny 180nm design kit & sample designs
    included. Let us know through the feedback button what you think of
    it.

    John Gianni
     
    John Gianni, Nov 3, 2004
    #5
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