VHDLIn in Cadence

Discussion in 'Cadence' started by jowong1, Dec 18, 2006.

  1. jowong1

    jowong1 Guest

    Hi all,

    I have copied the full adder design from "Guide to VHDL In for Design
    Framework II" and imported the vdhl code into cadence to generate a
    schematic. But I am not sure how I would simulate that schematic (there
    is no stimuli). I have tried a couple things but they keep giving me
    errors like cannot decent into behavior cellview (while the view is
    there). I was wondering if anyone out there can tell me how you
    simulated using AMS.

    Thanks
     
    jowong1, Dec 18, 2006
    #1
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