VHDL-AMS: assert as simultaneous statement

Discussion in 'Cadence' started by yaveh (Yet Another Vhdl Engineer Hoping), Nov 3, 2006.

  1. yaveh (Yet Another Vhdl Engineer Hoping)

    yaveh (Yet Another Vhdl Engineer Hoping) Guest

    Hi,

    I consider good design practise to write case statements with a
    default 'others' choice to be able to catch design errors and
    properly mark them with an assert statement.

    This works fine with VHDL sequentials and concurrent assert statements.

    However, I can´t get VHDL-AMS simultaneous assert statement to work.
    My tool complain with "unknown concurrent/simultaneous statement "
    when I write, e.g.:

    architecture [...] of [...] is
    shared variable a : [...]
    [...]
    begin
    [...]
    case a use
    when a1=> v'dot == -G - v**2*Air_Res; ;-- e.g.
    when b2=> [...]
    when others =>
    assert false report "case defaulted!" severity failure;
    end case;
    end;

    If you use VHDL-AMS, don´t you find it necessary?
    I just can´t find thsi construct in the Quick Reference of several
    VHDL-AMS Simulator...
     
    yaveh (Yet Another Vhdl Engineer Hoping), Nov 3, 2006
    #1
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