Hi, I have a synthesized verilog netlist (created using Synopys Design Compiler) that I would like to bring in to cadence so I can do place and route. However, whenever I try to use it, it does nothing at all. It claims to start and finish, but when I look at the log file, it just says "End of logfile" and there is no schematic created in the target library. I have even paired down the verilog to have only a single OR gate within the module description and I get the same results. The reference library does exist and only cells from the reference library are used. Does anyone have *any* suggestions at all? I'm getting very frustrated with no information at all in the log files... Thanks in advance! nigel.