Veriloga

Discussion in 'Cadence' started by greendays_01, Jan 3, 2007.

  1. greendays_01

    greendays_01 Guest

    Hi,

    I am implementing a DGMOSFET model in Veriloga. The program is quite
    long (more than 1000 lines), and I guess there are about 40 internal
    variables. So will this create any problems? (since most of the
    veriloga programs are very short)

    Thanks

    Chris
     
    greendays_01, Jan 3, 2007
    #1
  2. greendays_01

    Andrew Beckett Guest

    Well, if you have many instances, it could end up being quite slow...

    That said, there's a lot of work going on to improve verilog-a performance in
    spectre when using verilog-a for compact device models. So I'd suggest using
    a recent spectre version (e.g. MMSIM611).

    Regards,

    Andrew.
     
    Andrew Beckett, Jan 9, 2007
    #2
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