Veriloga simulation doesn't run

Hi,
I've built basic op-amp, and tried to run it in analog environment
using spectre simulator. The compilation passed ok, but i've got an
error that the simulator cannot descent into the cell and make a
netlist from any cellview though "veriloga" was defined as one of the
cellviews to be simulated. Are there any prerequisites (such as
services to be installed) to run this simulation?

Thanks,
Dmitriy

 

Hi Dimitry,

There are no special requirements to run verilog-A with Spectre.
I can hardly comment on your problem though, you seem to be having
veriloga in your switch view list.
Would you mind to confirm that:
1. You have successfully created and compiled your verilogA file and
you have created the corresponding symbol.
2. You have created a schematic testbench where you did instantiate
the symbol associated to your verilogA design.

Variable CDS_Netlisting_Mode=Analog must be set even though I can't
see any relation with the above error message. Off the top of my head,
this variable is setup by default with 'icms', not 'icfb'.

Any details you provide are likely to help debugging your case.

Cheers,
Riad.

 

Hi Riad,
thank you for your answer.
I think I mislead you. When I looked deeper into the problem I found
the next errors:
1) Failed to compile ahdlcmi module library ".../veriloga/
veriloga.va.ahdlcmi/obj/Linux2.6.9-70ELsmp+gcc/optimize/libahdlcmi.so"

2) In file ".../veriloga/veriloga.va.ahdlcmi/ahdlcmi.out", the
following error appeared:
/freespace/tools/Cadence/2006/IC_5.1.41/tools.lnx86/systemc/gcc/
install/bin/ld
cannot open crti.o: Nosuch file or directory
collect2: ld returned 1 exit status

I suspect that some environmental variables are missing. Am I right?

P.S.: I've compiled veriloga simply by creating a symbol and creating
symbol view from veriloga. Is there another way to do it?

 

shurin wrote, on 06/22/09 19:17:

You need to have the "glibc-devel" RPM package installed in Linux.

I believe however that if you were to use a newer version of spectre (e.g. an
MMSIM release, which is really advisable) it wouldn't have this problem.

Note that it should still run even without this - it just will fail to compile
the VerilogA (which helps for performance reasons). You could turn off the
warnings by doing:

setenv CDS_AHDLCMI_ENABLE NO

but I'd really recommend you just move to a newer MMSIM version (e.g. MMSIM71).

Regards,

Andrew.