veriloga model of opamp

Discussion in 'Cadence' started by wolf6873, Jun 21, 2006.

  1. wolf6873

    wolf6873 Guest

    hello everyone,

    I am trying to write a opamp model with verilog-A, there is a model
    from ahdlLib, however, I want something diff in with diff out and now I
    am stucked to how to define the output stage with Common-mode voltage.
    Any suggestions?

    Regards,

    Norman
     
    wolf6873, Jun 21, 2006
    #1
  2. wolf6873

    quek.geo Guest

    Hi

    There is a diff-in diff-out amp in the bmslib called "DiffOpamp". : )

    $CDSHOME/tools/dfII/samples/artist/bmslib
     
    quek.geo, Jun 22, 2006
    #2
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