veriloga -> loop of rigid brqnches (shorts)

Discussion in 'Cadence' started by Ben, Nov 25, 2005.

  1. Ben

    Ben Guest

    I would realise a polarisation stage in veriloga language.
    I need to instantiate 80 similar polarisations stages (PolaStage<79:0>).
    Each stage has the same input current (in) but not the same output
    voltage (out<79:0>).
    So if I have a current source of 80µA, each stage see only 1µA.

    To simplify my problem, I wrote :


    the parser didn't see error but when I start spectre, I have a fatal error :

    The following branches form a loop of rigid branches (shorts) when added
    to the circuit :
    PolaStage_0:in_flow (from in to 0)
    PolaStage_1:in_flow (from in to 0)
    PolaStage_2:in_flow (from in to 0)
    PolaStage_3:in_flow (from in to 0)
    .....

    Is it really impossible to write a veriloga close to the schematic in
    this case ??
    Thanks for your help

    Ben
     
    Ben, Nov 25, 2005
    #1
  2. Ben

    Andrew Beckett Guest

    To avoid re-saying the same thing, I answered this at:

    http://www.designers-guide.org/Forum/?board=verilogams;action=display;num=1132929989

    Andrew.
     
    Andrew Beckett, Nov 28, 2005
    #2
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. AHDL vs. Veriloga

  2. Pushing simulator session variables into veriloga models?

  3. VerilogA Debug

  4. running C functions from verilogA

  5. Assura RCX extraction with shorts ?

  6. How to get shorts

  7. LVS and Shorts in Virtuoso schematics?

Loading...