Hi, I am new to verilogA and am trying to debug a simple block using hdldebug tool. Once I give the Debug Netlist File from the main menu, the simulator does start, but then it gives errors like - Notice from spectre during circuit read-in. "/home/student/vineet/AMS/Thesis/ad_conv/veriloga/veriloga.va" 3: Illegal character ``' in input ignored. Error found by spectre during circuit read-in. "/home/student/vineet/AMS/Thesis/ad_conv/veriloga/veriloga.va" 3: Syntax error in specification of `include'. The statement that its refering to is `include "discipline.h" `include "constants.h" As far as I know this is the syntax for include statment...if I am wrong about that please correct me ! regards, Vineet.