VerilogA Debug

Discussion in 'Cadence' started by Vineet, Feb 18, 2004.

  1. Vineet

    Vineet Guest

    Hi,
    I am new to verilogA and am trying to debug a simple block using
    hdldebug tool. Once I give the Debug Netlist File from the main menu,
    the simulator does start, but then it gives errors like -

    Notice from spectre during circuit read-in.
    "/home/student/vineet/AMS/Thesis/ad_conv/veriloga/veriloga.va" 3:
    Illegal
    character ``' in input ignored.
    Error found by spectre during circuit read-in.
    "/home/student/vineet/AMS/Thesis/ad_conv/veriloga/veriloga.va" 3:
    Syntax
    error in specification of `include'.

    The statement that its refering to is

    `include "discipline.h"
    `include "constants.h"

    As far as I know this is the syntax for include statment...if I am
    wrong about that please correct me !

    regards,
    Vineet.
     
    Vineet, Feb 18, 2004
    #1
  2. Vineet

    Erik Wanta Guest

    Vineet:
    Are you using the tick mark that is slanting left (under the ~ in
    upper left hand corner of keyboard) and not a single quote in the
    `include?

    If you are using IC50 I think the extension on the discipline and
    constants files is .vams instead of .h.
     
    Erik Wanta, Feb 19, 2004
    #2
  3. Vineet

    Vineet Guest

    Hi Erik,

    No, that was the 1st thing I chked. I am using the correct tick ( the
    one below ~ ). Infact its a code generated by Cds ModelWriter, so I
    dont see how it could be wrong !! Besides, this is not the only error
    that I am getting. The log is real big, and it seems to find error
    with every statement in the code.

    regards,
    Vineet.
     
    Vineet, Feb 20, 2004
    #3
  4. Vineet

    Erik Wanta Guest

    Vineet:
    Does the code simulate but the hdldebugger doesn't seem to work?

    Are you starting the debugger from artist or are you running from the
    command line? I am thinking that if you are running the debugger
    command line it can't find the discipline.h and constants.h files for
    some reason.
     
    Erik Wanta, Feb 22, 2004
    #4
  5. Vineet

    Vineet Guest

    Hi Erik,
    I am starting it from unix prompt in the directory where I have the
    file. Yes, I get what you are saying about not finding the header
    files. Coz I dont see any files like ams.env that is used in AMS
    Environment which has specific reference to the header files -

    amsDirect.vlog includeFiles string
    "(disciplines.vams)(constants.vams)".

    So am I supposed to put something similar for verilog-a ? I see an
    INCA_lib directory with some .pak files. But they dont seem to be env
    files.

    regards,
    Vineet.
     
    Vineet, Feb 24, 2004
    #5
  6. Vineet

    Erik Wanta Guest

    Vineet:
    An environment variable by the name of CDS_VLOGA_INCLUDE can be used
    to point to veriloga include files. You might try this or run the
    veriloga debugger from analog artist. Or use the AMS Designer
    debugger if you have access to that.
     
    Erik Wanta, Feb 26, 2004
    #6
  7. Vineet

    Vineet Guest

    Hi Erik

    Ya, thats what I am doing now. I have access to the Cadence AMS
    Environment and the related tool set. I hit a bottleneck again ! I
    have posted the question in the group regarding that ( Sub - spectre
    model files). Can you please throw some light on that.

    Thanks,
    Vineet.

    "Bottlenecks are challenges, not setbacks" - Myself :).
     
    Vineet, Feb 27, 2004
    #7
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