verilog-XL global force or reset

Hello,

I'm trying to use verilog-XL to simulate a circuit from within the
Verilog-XL Integration for Composer environment. My schematic includes
instances of flip-flops from a standard cell library that do not have
any sort of reset pin. My circuit includes several things like
flip-flops configured as divide by two blocks. The problem of course
is that initially the output is an 'x' and since the input comes from
the output, the 'x' never resolves into known logic states. There are
quite a few of these at several different levels of the hierarchy so it
would be a huge amount of effort to enumerate all of the nodes into a
huge list of force/release lines.

So my question is if there is a way in verilog-XL to globally tell it
that all reg's should be set to 0 initially (or 1, I don't really care,
it really doesn't matter what state this thing comes up in for my
simulation or in real hardware).

Again, its not like I'm generating a flip-flop with something like

always @posedge(clk) begin
d <= ~d;
end

where I could modify it to have a reset for simulation puposes.


I have stuff more like this:

DFFX1 I1 (.CLK(clk), .Q(q), .D(d));
INVX1 I2 (.Y(d), .A(q));

and DFFX1 and INVX1 are from the standard cell library I have to work
with. In other words its just a verilog netlist as opposed to a
synthesizeable behavioural description.

Thanks
-Dan