Verilog problem: default case to set signal xxxx

Hi all,

I always found people like to add default branch like below:
case(branch)
... ...
[all the possible branch]
... ...
default: signal = 8'bx;

And my friend told me it's for simulation cause. When branch not hit
all the possible case, the branch must have something like xxxx. So we
set signal to xxxx to let xxxx pass go on and help us to find the bug.

If I set default: signal = 0; the xxxx problem will be hidden and hard
to find the bug.

But as we know, there is no xxxx signal in real digital world. So is
there any better method to solve the problem?

Best regards,
Davy

 

What is the problem with this? It does not matter that this doesn't
correspond to a real world value. The synthesis tool will see that it
is a don't care, and hopefully should optimise the logic accordingly,
giving you the smallest / fastest circuit.

Cheers,
Jon

 

In addition to "xxxxx" there may be some other choices.
1. (simulation debug) Use $display instead of signal assignment, for
example:

default: $display ($time,"<%m> ERROR: non-speicified branch is
taken");

Synthesis tools drop all $display statements, while simulators report
about an error in a runtime. It eliminates the need to observe "x" on
selected signals in the waveform viewer. Also, in some cases "x" may
propagate to "signal" from the previos logic (such as unitialized
memory arrays). Use of "$display" will isolate bugs better.

2. (emulation debug) Create observable error status register, associate
each one of register's bit with different "case" statements and set
them to "1" when corresponding default branch is taken:

default: uncomplete_case_reg[0] <= 1'b1;

Finally, some synthesis tools (such as Synopsys DC) produce warnings
for case statements in which not all possible cases are covered. To get
this reporting, you have to use pragma "// synopsys full case" with the
case statement.

Regards,
-Alex

 

This sort of thing can end up with lots of false positives though, that
can obscure the real bugs. (i.e. you'll get lots of these printed
before reset, etc)

Cheers,
Jon

 

I agree with Jon. Most of the comments in this thread are related to
simulation, but finally we design the circuits with HDL languages to
synthesize them. Setting x to the default case also lets the synthesis
tool produce faster/smaller circuits, because the synthesis tool has in
that case the freedom to optimize the circuit according to internal
optimization algorithms.

It also can make the design more robust, because the verification
engineer will try to remedy the case and thus design bugs can be
localised better (probably at the expense of time to debug, which is
worth having it).

Utku.