Verilog-A vector syntax

Discussion in 'Cadence' started by compact, Feb 20, 2004.

  1. compact

    compact Guest

    Hi,
    I'm wondering if the following vector expressions are Valid with
    VerilogA:

    _ branch (out[3],in[3]) net; // LRM says 'range' ??
    _ V(out[3],in[3]) <+ I(out[3],in[3]);
    _ I(<in[1]>)

    Thanks for any inputs,
    Lionel.
     
    compact, Feb 20, 2004
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. Sorting Rectangle Vector List

  2. Raster to Vector (Text identification)

  3. Where I can get or buy BSIM3v3 model file in Verilog-a or Verilog-ams?

  4. Where I can get or buy BSIM3v3 model file in Verilog-a or Verilog-ams?

  5. I-Q FIR filter using verilog/verilog-a gives no output on one channel

  6. how to make Verilog netlist without a Verilog license

  7. problem with verilog-in in when using arithmetic shift in verilog vode.

  8. Verilog-A syntax error

Loading...