Verification for a big chip???

Deat all,

If I design a big chip that includes several parts (layout) designed
by different groups, I can consider each part as a cell and do P&R and
fit it into a Padframe.

But I have a question about verification,

How can I do timing analysis and power analysis for the entire chip?If
I extract the netlist for the entire chip and do circuit level
simulation in Hspice, the simulation speed is too slow. What is the
good way to verify the entire chip in industry?

Thanks,

Adrian

 

Oh boy, you are defnitely singing my tune! We too have this same problem
when we design larger circuits, and are looking for a solution. Spectre and
HSpice are definitely a pretty good way to get a good look at what is going
on, but it does take alot of time and horsepower(and memory). The thing we
usually do is break it into smaller blocks and do an analog simulation on
the critical areas. I have used Verilog in the past to simulate basic
delays extracted from analog simulations, but that won't give you power or
drive numbers.

I too would be curious as to what other folks do. Our designs are mainly
digital that operate from DC->80Gbps, so analog simulation is a must, and
extracted parasitics from the layout is a must! Our flow right now is to
use Composer for the schematic, LayoutXL for layout and Analog Artist(HSpice
or Spectre) for simulation while using Diva for verification.