VDD 0,35 um

Hi!

Can anyone tell me why should I use VDD=3.3 V when I'm using the 0,35
um technology? Can I use 5 V instead of 3.3 V?

Thanks

 

Can anyone tell me why should I use VDD=3.3 V when I'm using the 0,35

Because higher voltages can cause breakdown of the gate oxide.

You may have thick gate oxide transistors available for 5V operation in your process, though. But
they will be slower. These're typically used for I/O cells.


Stéphane

 

Dear Sykab,

Your PDK documentation (DRM, Electrical Rule Manual ...) should tell
you the allowed voltages on each node of each transistor.
A kind of data-sheet that tells you for example :
VGS(NMSO1) = 3.3v +/- 10%
VDS(NMSO1) = 3.3v +/- 10%
.... etc

As Stéphane explained, the Voltage you put on the transistor's gate
depends on the Oxide thickness (Tox), The thickest it is, the more
voltage it supports.

But, what really happen if you put 5V on your transistor that supports
3.3V ?
In the real world, your transistor will burn up on die ... In the
simulation world, it may work, it may not, depends on how your model
has been derived.

When I was working with the STMicroelectronics PDK using Eldo (Mentor
Graphics Simulator), the Spice Model cards used to come with Safe
Operating Area Checks statement, something like :
.setsoa label="VGS out of range" e V(G,S)=(-2.75,2.75)

So when you simulate your design including the Check of Safe Operating
Area (. checksoa eldo command in you netlist), the simulator raises
warnings/errors if your VGS exceeds the defined limits at some point
during the simulation. This is the kind of range checking that helps
designers in avoiding any unlucky biasing.

I know that spectre supports a similar thing but I prefer to send you
to the Spectre doc since I have never used it myself :
-> Virtuoso® Spectre® Circuit Simulator UserGuide -> Control
Statements -> Assert Statement
Andrew can tell more about this.

Cheers,

Riad.