hi all, As i am new to cadence, previously i had a problem on how to simulate the digital-control logic along with the analog in cadence. I finally came to know a flow in which i could do the simulation. First synthesizing the vhdl design in synopsys environment and dumping out the verilog netlist. and then importing this verilog netlist into cadence and making its symbol using VerilogIn. Hope I am right? It would be great if any one could comment on this. Now I have a doubt, how do i tell cadence, the stadard-cell library which i had used to map the digital design, Is this The " Reference Library" In this VerilogIn window. if so how do i do it, in which format. Thanks a lot.