Using a new standard cell library with Synopsys Design Analyser

Hi All,
I have a few VHDL designs which I want to synthesize using Synopsys DC
and write them out as structural verilog netlists. I also have a
standard cell library, the cells of which, I want use to actually
create the layout of the design.
For experimentation I used the library class.lib provided with the tool
to generate the netlist. But now so that the tool uses the gates and
cells available in the standard cell library, do I need to form a new
".lib" file and convert it into .db and provide it as the link library
and target library?
As a matter of fact, I tried doing this. I just replaced the names of
the cells in class.lib, with the names of the cells in the standard
cell library, the functionality remains the same. Then I used Library
Compiler to form the .db file and also changed the .synopsys_dc.setup
file to use this library before starting Design Analyzer. DA does not
give any errors in linking or compiling the design but it does not
write it out. I was wondering if there were other settings that need to
be done.

I would really appreciate your help.

Thanks,
FV

 

I am sorry, this is more of a synthesis question than a cadence related
one.