umc 0.18 um corner analysis

Discussion in 'Cadence' started by Sabyasachi, Aug 17, 2009.

  1. Sabyasachi

    Sabyasachi Guest

    I want to do corner analysis in umc 0.18 um technology in caadence

    the model files required for umc are

    modelFile(
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    core_rf_v2d4.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    io_rf_v2d3.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    l_slcr20k_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    mimcapm_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_MIMCAP_V101.lib.scs" "mimcaps_typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_REG18BPW_V123.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_REG18_V124.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_REG33BPW_V123.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_REG33_V114.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_RES_V133.lib.scs" "res_typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_ZVT18_V121.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_ZVT33_V113.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_LVT33_V113.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_LVT18_V113.lib.scs" "tt")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    pad_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    rnhr_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    rnnpo_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    rnppo_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    vardiop_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    varmis_18_rf_v2d3.lib.scs" "typ")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_BJT_V112.mdl.scs" "")
    '("/usr/local/cadence/umc/UMC_18_CMOS/../Models/Spectre/
    MM180_DIODE_V113.mdl.scs" "")
    )

    now there are two kind of files one containing 5 sections tt ss ff sf
    fs
    and another type contains 3 sections
    typ min max

    for the first kind it is easy to determine which section to use in
    which corner
    but for second type of files which section(typ min max) i should use
    for which corner.
    please help

    Report msg +5pts

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    EDAboard.com Forum Index -> Analog IC Desig
     
    Sabyasachi, Aug 17, 2009
    #1
  2. Sabyasachi

    Riad KACED Guest

    Hi,

    What is your question ?
    What is it that confuses you ?

    In summary, for MOS transistors, most foundries provide corners for a
    Typical, a Fast and a Slow transistor. This would then lead to corner
    such SS where both Nmos and Pmos are in a Slow mode ... etc. But for
    passives, say resistors, foundries typically release Typ, Min and Max
    corners. Simple as that !

    Best way to run the corners is to look at your design, ask yourself
    what is the output you are interested in and what are the devices that
    are likely to impact your signal path. Then you will be able to
    calculate the Best / Worst cases. Otherwise, just proceed as most
    designers, i.e. run all the corners ...

    A bit of thinking and optimization would save a great deal of CPU time
    and disk space ...

    Cheers,
    Riad.
     
    Riad KACED, Aug 18, 2009
    #2
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