UltrasimVerilog on Linux terminating due to a Segmentation fault signal

Discussion in 'Cadence' started by kentauta, Dec 22, 2005.

  1. kentauta

    kentauta Guest

    Hello all,

    I am trying to run a simulation with UltrasimVerilog on Linux.
    However, whenever I run a simulation, the simulation terminates saying
    "UltraSim is terminating, it received a Segmentation fault signal."
    after patitioning the circuit. The same circuit can be simulated
    without any problems with spectreVerilog, and normal Ultrasim
    simulations without Verilog cells work fine.

    Does anybody know how to solve this problem?

    Here is my CAD environment:

    CPU: Pentium 4 3.2GHz
    Kernel: 2.4.27-2-686-smp and 2.6.8-2-686-smp (both tested)
    Distribution: Debian
    Ultrasim Version: 6.0.1.118 32bit (in MMSIM60USR1)
    Verilog-XL Version: 05.40.003-s (in IUS54UPDATE1)

    Thank you,
     
    kentauta, Dec 22, 2005
    #1
  2. kentauta

    Andrew Beckett Guest

    I'd first try installing MMSIM60 USR2, and if that doesn't fix it (perhaps it's
    been encountered before), you should contact Cadence customer support.

    Regards,

    Andrew.
     
    Andrew Beckett, Dec 23, 2005
    #2
  3. kentauta

    kentauta Guest

    Hi Andrew,

    Thanks for your suggestion.
    I will talk to our system administrator.
     
    kentauta, Dec 23, 2005
    #3
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