TSMC 90nm library spice deck

Discussion in 'Cadence' started by Koustav, Nov 5, 2007.

  1. Koustav

    Koustav Guest

    Hello everybody,

    I needed the spice netlists for the library cells in the TSMC 90nm
    library. We had approached the cadence vendor for USF
    but they said they only provide front end files, i.e., .lef
    and .tlf(or
    ..lib) files, but no back-end files while includes the .sp files. Does
    synopsys
    provide this as well on request?

    I was wondering if somebody could help me out in obtaining this. The
    only
    other option for me is to use spice files for 180nm OSU library and
    scale it somehow...which will be tricky. Hand writing the spice files
    for the library will be too time consuming and I am trying to avoid
    that.

    I would really appreciate any help on this.

    Thanks,
    Koustav
     
    Koustav, Nov 5, 2007
    #1
  2. Koustav

    JD Guest

    Hi,

    I think you should contact TSMC directly.

    JD
     
    JD, Nov 5, 2007
    #2
  3. Koustav

    Koustav Guest

    Hi JD,

    Thanx for ur response. Do you know anybody who asked TSMC any time
    about their library spice decks? Do they respond? I heard vendors are
    really reluctant in giving away these...

    Thanks,
    Koustav
     
    Koustav, Nov 6, 2007
    #3
  4. Koustav

    JD Guest

    Hi,
    If you are not design company intend to tape out with the TSMC 90nm
    CMOS process, it takes quite long time to get the PDKs from them, and
    you need assign NDA with them.

    There is some other places you may get some models for TSMC 90nm
    process, such as MOSIS, you can go to their website and search it.

    JD
     
    JD, Nov 7, 2007
    #4
  5. Hi,
    are you doing real work or is this student work or just for fun? (Who
    do just for fun work with Cadence anyway?)

    You could also try the "50nm" technology that J. Baker is offering on
    his course homepage http://cmosedu.com
     
    Svenn Are Bjerkem, Nov 7, 2007
    #5
  6. Koustav

    Koustav Guest

    Hi JD,

    Thanx for ur suggestions. My problem is that all I needed was a tech
    library with all (libcells.sp, .lib, libcells.v, .lef ) files with
    different drive strengths. The OSU 180nm library provides these files
    but most cells in library does not have different sizes. I will try
    contacting TSMC/MOSIS directly then.... hope they turn out good.

    Thanks,
    Koustav
     
    Koustav, Nov 10, 2007
    #6
  7. Koustav

    Koustav Guest

    Hi Svenn,

    Thanx for ur suggestions. My problem is that all I needed was a tech
    library with all (libcells.sp, .lib, libcells.v, .lef ) files with
    different drive strengths/sizes. The OSU 180nm library provides these
    files but most cells in library does not have different sizes. Jake
    Baker is only providing the spice model file but not the transistor
    level implementation of a library in spice, and I also need
    the .lib, .libcells.v etc files for that library as well. I cud get
    even 22nm model file from BPTM no problem with that......

    Thanks,
    Koustav
     
    Koustav, Nov 10, 2007
    #7
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