Tool for Auto Layout Generation

Hi All,
I have a quick question here.
I have designed a circuit in Virtuoso Composer Schematics and I am
trying to generate a Layout. Is there any tool in Cadence that accepts
the schematic and generates the layout for the same including the
connections between the transistors? If yes, please tell me what tool
is to be used for the same.
Thanks,
Kumar

 

From your schematic do this
Tools -> Design synthesis -> layout XL.
HTH

 

Hi,
Thanks for the info. I did go through the same steps earlier and
was able to get the transistors individually only but was not able to
get the transistors connected to each other. Can you please tell me
how to get the auto routing done for a design?

Thanks,
Kumar

 

Under VXL there is menu called Route
Route -> export to Router.
( I am assuming you have access to the router. If it's grayed or absent
I may mean you don't have a license or it it is not installed)

 

Or check with your sysadmin if you have a tool called "neocell", that
would be more powerful than virtuosoXL.

Read the manuals when you use vituosoXL (also known as "DLE" or "DLP"
), else you ll get very surprised, or even frustrated.

 

Thanks a lot, I talked with my sys admin and found that we do have
license for Neocell and got it installed.
Now, I need to read all the documentation on generating a layout from
Schematic.
If there are any tips for the same, can you please tell me?

Thanks,
Kumar

 

(Kumar Yelamarthi) asked:

1. My Flow Engineering team explored and defined an ABC (analog block creation)
quick-block flow, using 100% Cadence tools (and our partners), last half
of the year, which I'll send you if you provide me a business email and
some indication of your maintenance support.

2. The ABC flow takes a simple VCO thru all the rapid-block-creation stages,
using Aprivia with Spectre to quickly determine the parameters for the
40 xtor circuit; to using NeoCell to quickly 'synthesize' the constrained
circuit (e.g., matching devices); to using Diva/Assura to verficy the
desing; and even to using DCM and other tools to finalize analog IP, e.g.,
to create LEF, LIB, TLF, GDSII, VerilogA, etc. for others to incorporate
your newly created (1 day) quick block using this abc flow.

3. My custom IC flow engineering team has also defined a more manual flow,
again using 100% Cadence latest tools, which employs Aptivia, UltraSim,
Virtuoso Composer, VirtuosoXL, Assura, VoltageStorm, Electron Storm, etc.,
(currently being piloted at Motorola & National Semiconductor) which is
also taught tomorrow, Sunday the 14th. of September, in New Hampshire,
at the International Cadence User Group conference:
http://www.cadenceusers.org

If you provide your business address, I can send you both, along with
the database for the second (the first is in the TSMC13LV process; the
second uses a PLL built on the Cadence generic process design kit
which has vastly fewer restrictions on primary distribution.).

JOHN GIANNI

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