to design new pdk ?

hi all,

i am a student pursuing M.Tech vlsi design india,we are having
complete cadence suite of tools here.doing a project for 1 micron fab.

i would like know some basic thing's on designing a PDK.

1. what are inputs needed from foundry to design a PDK ?

2. what is the flow involved in it ? what are the tools needed ?

3. whether it can be done only by a tool vendor in tie up with foundry
?

or in other words

If we (our university) have a complete foundry details and with our
cadence tools can we create our own ?

4.we are having cadence gpdk with us,is it possible to modify it to
other specific process ?, if can what documents in cdsdoc i have to
refer ?

5.In general what are the documents (in cadence cdsdoc ) or any web
link that i have to refer to get start with designing a PDK ?

with regards
selvakumar

 

wrote

Generally, it's easiest to simply use the Cadence process design kit
provided to you (your foundry has already blessed these kits).

These Cadence process design kits contain complete schematic symbols & CDFs,
Spectre models, layout pcells, layout technology files, layout
display.drf files, verification rule decks, etc.

Well, if you MUST do it yourself, pick up a copy of Cadence BSIM PRO (I think
that's what it's called) to generate the BSIM3 spice models. Once you
have the simulation models, design the schematic symbols using the Cadence
TSG text-to-symbol generator (this astounding tool will create symbols from
virtually ANYTHING, even just a pin list).

Once you have the models & symbols, simply bring up the Qcell forms to build
Qcells (instead of Pcells) which are a fantastically quick way to graphically
generate compiled Pcells (use the latest Cadence DFII 5.0 software on CDBA or
OpenAccess). Or, if you are a programmer jock, use the SKILL Pcell mechanism.
(There isn't anything you can't do in SKILL, except, maybe, solve world peace.)

Once you have Qcells or Pcells for nmos, pmos, resistors, capacitors, etc.,
you'll need rule decks for either Diva or Assura or Dracula (depending on
which tool you're using). We have translators which convert from one to the
other, so, best to write them up in Assura & just convert to the rest of
the formats, as desired.

All along, keep a running log of the items you've built; it will become the
documentation for the new process design kit you've built yourself. (Again,
it's MUCH EASIER to just use the one blessed by the foundry & supplied by
Cadence & tested with each outgoing release to ensure it still works well.)

Certainly is easier to obtain from the Cadence EDA vendor (who works closely
with the foundry, even to go so far as to make silicon on every release of
their software & to test the silicon accuracy with the Celestry tool set).

Certainly. It isn't worth it; but you can do it (as I explained above).
Again, why not just download the Cadence-supplied foundry kit from
http://www.cadencepdk.com or direct from the foundry?

I just logged in myself, and I see over 50 PDKs in my download screen.
Every process you'd need is there already, even the submicron ones.

I never read the documentation so I don't know about the docs; but there
are plenty of folks who design chips using the well-known generic process
design kit, & then port their generic design to a variety of processes. In
effect, they spend their energy optimizing & porting the topology (which is
vastly more efficient than battling every new process that comes along).
You'll need specialized tools for this approach though (look around, there
are tons on the market already, and more coming online every day).

Again, I never read the fine documents. But, I think Cadence posts CDSDoc
online at their http://sourcelink.cadence.com site (if I remember correctly).
I never go there, but, I've seen others post URLs pointing to the docs there.

In the end, you can build your own process design kit (but why not just pick
up the complete design kit from Cadence or from the foundry site)? Also, you
certainly can go generic and then optimize/port to the specific process (I
heard of a startup using the beta Cadence 90nm or 65nm process design kit for
exactly this task to develop a platform chip in the gaming space).

Good luck!
SS