Timing Optimization in Encounter

Hello all.

I am working on a microcontroller design using the Cadence tools and an
OKI 0.16 standard cell library. I optimized my design for speed as much
as possible before layout using the Synopsys synthesizer to analyze the
critical path. The Synopsys and PrimeTime tools estimated the design
would run at a maximum clock rate of 250MHz. I then used SOC Encounter
to create a layout. After creating a floorplan, running place, trial
route, and optimize in Encounter I ran a timing analysis. The timing
analysis indicates that the design will run at a maximum clock rate of
180MHz (much slower than the Synopsys estimate). Is that much of a
difference between pre-layout and post-layout timing expected? Can
anyone suggest a way to get the final layout to perform more closely to
the Synopsys estimate?

Thanks.
Laura

 

I'm not an Encounter guy (I just took the RTL Compiler training out of
sheer curiosity), but have you tried putting the RTL through RTL
Compiler and seeing how it compares with the Synopsys numbers?

One of the remarks that struck me from the training is, "The netlist
matters." Could it be that the netlist being fed from Synopsys to
Encounter is suboptimal for it? Did a false path get dropped in the
translation? Is it just one net holding you back, perhaps something you
could toss an inverter in the middle of?

The other approach would be to fix the Synopsys tools to get *their*
output to correspond more closely to the layout numbers, but I don't
think that's a solution you wanted to hear.