time gated pwl

Hi All,
I'm using spectre (mmsim-6.2) to simulate a PLL.
I have a customer supplied PWL noise file which starts at say 10us.
The noise file is to be used to excite the power supply of a PLL. I
would like to make the start of the noise to be dependent on a PLL
locked signal instead of waiting 10us before exciting the supply since
across corners, the PLL may lock much faster than that. I have thought
of using a network of ideal switch elements to switch in the noise,
but that would require the noise stimulus to be active all the
time(although disconnected) which will slow down the sim quite a lot.
A verilog-a gated pwl source would be ideal, but I haven't been able
to come up with one.

Does anyone have any ideas?

Thanks,
Barry

 

Barry,

Did you search the: http://www.designers-guide.org ?
There are many Verilog-A/MS modeling examples.

Riad.