Tie logic values to vdd/gnd within Encounter

Discussion in 'Cadence' started by Andreas, Apr 2, 2008.

  1. Andreas

    Andreas Guest

    Hi,

    I'm using Encounter for Place & Route of a synthesized verilog netlist.
    The problem is that the synthesis tool (BuildGates) created assignments
    such as:

    module m(dout);
    ouput [0:15] dout;

    assign dout[15] = 1'b0; // <--- problem

    (...)

    But Encounter doesn't connect the net dout[15] which has the fixed value
    1'b0 to the vdd net, although I used the following commands within Encouter:

    globalNetConnect vdd -type tiehi -module {}
    globalNetConnect gnd -type tielo -module {}

    I already tryed to insert tiehi/tielo cells, but I cann't find any
    tiehi/tielo cells within my synthesis libraries.

    How can I tell Encounter to connect 1'b0 to gnd and 1'b1 to vdd?

    Thanks,

    Andreas
     
    Andreas, Apr 2, 2008
    #1
  2. Andreas

    Muzaffer Kal Guest

    This seems necessary but pay attention to the case of the VSS/VDD
    nodes. I think they have to match the power/ground pins of your
    standard cells so look at your LEF to make sure. Also you probably
    don't need to module constraint there.

    Also assuming you're using Nanoroute the following option should be in
    your TCL file:

    setNanoRouteMode -routeAllowPowerGroundPin true

    Otherwise Nanoroute doesn't know what to do.
    Muzaffer Kal
    ASIC/FPGA Design Services
    DSPIA INC.
    http://www.dspia.com
     
    Muzaffer Kal, Apr 2, 2008
    #2
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