Is it possible to use SystemVerilog in mixed-signal simulations with AMS?
Hi Adam, Yes it is possible. Start by creating a verilog view in your CDS DFII session and then paste your systemVerilog code into the editor. This would create a symbol for your design if it is correct. The next step is to compile your code within AMS designer using the ncverilog option -sv. Option -ams for digital blocks compile should be disabled. A quick search in the designers guide form comes with a thread that might interest you: http://www.designers-guide.org/Forum/YaBB.pl?num=1171882045 This post is 2 years old however and I don't know which version of IUS you are using. You have better looking at the doc of your IUS stream or probably post it. Regards, Riad.
