symbol + schematic pcells

Discussion in 'Cadence' started by S. Badel, Oct 26, 2005.

  1. S. Badel

    S. Badel Guest

    Hi all,

    We've designed a schematic pcell which includes a variable number of
    instances. Also, the I/O pins are busses whose size varies according to
    some "width" parameter.

    We created also a symbol pcell with the varying pin width so that the
    terminals on the symbol and the schematic match.

    When we instanciate the symbol, the pin width come right. When we
    instanciante the *schematic* we also see the pcell evaluated correctly.

    What we would like is to be able to use the symbol in a schematic, and
    expect the netlister to switch into the evaluated submaster of the
    schematic pcell. This doesn't work, that is, the port list appears
    correctly in the netlist but the inside of the subcircuit is always
    netlisted the same regardless of the parameter values.

    Are we missing something here ?

    thanks in advance

    stéphane.
     
    S. Badel, Oct 26, 2005
    #1
  2. S. Badel

    Trevor Bowen Guest

    I have developed pcells that have similar functionality for current
    mirrors and diff pairs, where both the schematic and symbol are
    evaluated dynamically based on a "numberOfOutputs" parameter.

    In doing this, I ran into a possibly related bug in schematic pcells -
    they are not always evaluated unless a certain events are triggered.

    I never did figure this out completely, but the pcell was always
    evaluated successfully if it involved a change in the number of pins,
    number of instances, or other major structural changes. However, if I
    tried to perform calculations and update fields on the children
    instances, that would not work. It seems that a new sub-master was not
    created unless there was a required _structural_ change. If _only_
    changes to properties were required, a new submaster was not created,
    and the default values were used. However, if the new sub-master would
    require changes to the number of instances, pins, etc., then the
    properties would have the correct values.

    It seemed like a bug to me, but submitting a SR rolled off my TODO list,
    because I was pushing for a deadline. So, I calculated the necessary
    data in the form callback and passed the data through pPar's for hidden
    parms.

    Hope this helps...
     
    Trevor Bowen, Oct 26, 2005
    #2
  3. Are you both using IC50 or later? Schematic pcells did not netlist properly
    until then - it did not correctly handle the variant generation at netlisting
    time.

    These days it seems to work OK - I've done a couple of these in the last year or
    so, and they netlisted fine. One which had a bus with variable width, for
    example.

    Regards,

    Andrew.
     
    Andrew Beckett, Oct 27, 2005
    #3
  4. S. Badel

    S. Badel Guest

    Are you both using IC50 or later?

    Yes, IC5033USR3 exactly.

    If you couldn't spot any obvious mistake in the explanation, then it should work...
    I will try it again.

    thanks,

    stéphane
     
    S. Badel, Oct 28, 2005
    #4
  5. S. Badel

    S. Badel Guest

    If you couldn't spot any obvious mistake in the explanation, then it
    Finally, I sorted it out. Not sure exactly how, but recompiling the pcell
    from scratch helped.

    Thanks for your input,

    stéphane
     
    S. Badel, Oct 28, 2005
    #5
  6. S. Badel

    Trevor Bowen Guest

    I was using IC5.1.41, IC5.0.33 at the latest (or earliest :)
     
    Trevor Bowen, Oct 31, 2005
    #6
  7. Well, I'm surprised. Can you log this with customer support?

    Regards,

    Andrew.
     
    Andrew Beckett, Oct 31, 2005
    #7
  8. S. Badel

    Trevor Bowen Guest

    It's on my TODO list. :)
     
    Trevor Bowen, Oct 31, 2005
    #8
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