Substrate Noise Analyst

Discussion in 'Cadence' started by Allen, Apr 20, 2005.

  1. Allen

    Allen Guest

    Hi,

    Can any one tell me how to do the configuration for Substrate Noise
    Analyst? We have it installed, but no one knows how to configure and
    use it.

    Thanks.

    Regards,
    Allen
     
    Allen, Apr 20, 2005
    #1
  2. Allen

    G Vandevalk Guest

    When I used it (long time ago ... ) the key input was a 2d description
    of the cross section of the chip with a resistivity per layer
    .... and a clean lvs
    .... and a dependance on the global 0! substrate
    .... ;^(

    - G
     
    G Vandevalk, Apr 21, 2005
    #2
  3. Allen

    fogh Guest

    Yuck !

    This and other careless IC models (including pads ESD , etc..) abusing
    node zero are discouraging those few last brave designers who have the
    will to simulate a chip within a package with external components and an
    external ground.

    Node zero is baaad , M'kay ?
     
    fogh, May 3, 2005
    #3
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