Std cell routing Stratgey

Steve,

For your info .

Using moat as interconnect
Minimize moat area in order to minimize capacitive load
Minimize wire length
Combine cells.
External routin
Gate connected via a metal helps for quick redesign with metal
only.If metal3 is used by the design: Experience shows that not
using metal 3 but metal 1 and metal2 inside the cells to preserve
routing space for power doesn't pay out.

Another good strategy is to not use metal2 and metal3 at all
inside the cell or at least in one part across the cell. Thus, the
router can utilize that region for metal2, via2, and metal3
interconnect between the cells.

By using chain of metals inside the cell starting from the cell pin:

A short piece of top metal going down with a via to next short
piece of metal and up again to a small top metal piece. This puts
a break for long metal leads. Thus, you won't get new problems
from the outside of the cell after chip routing.


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| |__<*> ___ Tracy Groller | Texas Instruments, Inc.
| _|III|_ | ------------------| Wireless RFCMOS Design
_____| /_ III _/ \ TI MSGID: TAG2 | P.O. Box 660199, MS 8729
\_ /III/ | PC Drop: PFLL | Dallas, Texas 75266
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this is an mis-post please disregard.

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\ ~ ~ ///
---- ( @ @ )
| | ======oOOo==(_)==oOOo=======================================
| |__<*> ___ Tracy Groller | Texas Instruments, Inc.
| _|III|_ | ------------------| Wireless RFCMOS Design
_____| /_ III _/ \ TI MSGID: TAG2 | P.O. Box 660199, MS 8729
\_ /III/ | PC Drop: PFLL | Dallas, Texas 75266
\ _ /III/ _| -------------------------------------------------
\_/ \ \___> - Phone: (214) 480-2217 Text Pager
\ / Email:
\ \ =======================================================
\---\