Spectre simulation question

Discussion in 'Cadence' started by ÎâÆóÖÜ\(sanguine\), Aug 12, 2004.

  1. Hi All
    I have a question about the simulation by spectre.

    When I simulate a netlist for transient analysis, a fatal error will be report at one time . The error message is "fatal error found by spectre during transient analysis tran".

    Who can tell me the reason of the error and how to resolve this question.
    Thanks very much

    Best Regards
     
    ÎâÆóÖÜ\(sanguine\), Aug 12, 2004
    #1
  2. ÎâÆóÖÜ\(sanguine\)

    S. Badel Guest

    excuse me but you should look further down in the log
    file.
    typically spectre will complain with the message you described,
    followed by an explanation.
    if you can't figure out just post the log file.

    st¨¦phane
     
    S. Badel, Aug 12, 2004
    #2
  3. ÎâÆóÖÜ\(sanguine\)

    harry Guest

    Hi stephane,
    possible problem is that u messed up ur timing on the pwl's or
    voltages sources.
    or u made some changes in design and didn't save it.and ran ur
    simulations.
    Also check ur output log or CIW window for error messages.It should
    tell u what the problem is.

    regards

    Harry
     
    harry, Aug 17, 2004
    #3
  4. ÎâÆóÖÜ\(sanguine\)

    Sajan Guest

    Hi
    I am having a problem with spectre simulation.

    Fatal error found by spectre during topology check.
    The following branches form a loop of rigid branches (shorts) when
    added to
    the circuit:
    TOP.TEST1:SUS_DRVR_EN_flow (from TOP.SUS_DRVR_EN to ground)
    TOP.TEST1:pAD_DP_flow (from TOP.PAD_DP to ground)
    TOP.TEST1:VSSA_PSUB_flow (from TOP.VSSA_PSUB to ground)
    spectre terminated prematurely due to fatal error.

    This is what I see.

    But all the signals mentioned in the log are just being driven by me
    in the testcase as

    V(SUS_DRV_EN) <+ 0;
    V(PAD_DP) <+ 1.2;
    V(VSSA_PSUB) <+ 0;

    So can anybody help me why I am getting this error???
    Thanks,
    Sajan.
     
    Sajan, Aug 19, 2004
    #4
  5. Are there any connections above which complete the loop?

    Andrew.
     
    Andrew Beckett, Aug 19, 2004
    #5
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