spectre output hierarchy sep strangeness

Discussion in 'Cadence' started by danmc, Jan 25, 2005.

  1. danmc

    danmc Guest

    Sometimes I run a spectre sim and get outputs like

    v("VDD"), v("I1.MYSIG")

    and other times I get

    v("/VDD"), v("/I1/MYSIG")

    what the heck makes this change and how can I prevent it? It makes
    managing ocean scripts for automatic plotting of various signals a
    major pain.

    Thanks
    -Dan
     
    danmc, Jan 25, 2005
    #1
  2. danmc

    Mr . SJ Guest

    Not sure is this helps: Page 26 of the ocean ref manual inside cdsdoc:


    outputs() in OCEAN
    Throughout this manual are examples of nets and instances preceded by a
    "/" as well as
    examples without the "/". There is a significant difference between
    the two.
    If you create a design in the Cadence® analog design environment and
    save the OCEAN file,
    all net and instance names will be preceded with a "/", indicating
    they are schematic names.
    The netlist/amap directory must be available to map these schematic
    names to names
    the simulator understands. (If your design command points to the raw
    netlist in the netlist
    directory, the amap directory is there.)
    OCEAN Reference
    Introduction to OCEAN
    If you create a design or an OCEAN script by hand, or move the raw
    netlist from the netlist
    directory, the net and instance names might not be preceded with
    "/". This indicates that
    simulator names are used, and mapping is not necessary.
    If you are unsure whether schematic names or simulator names are used,
    after
    selectResult( S_resultsName ), type outputs() to see the list of net
    and instance
    names.
    Note: Although you can move the raw netlist file from the netlist
    directory, it is not advised.
    There are other files in the netlist directory that are now required to
    run OCEAN.
     
    Mr . SJ, Jan 25, 2005
    #2
  3. danmc

    Mr . SJ Guest

    Not sure is this helps: Page 26 of the ocean ref manual inside cdsdoc:


    outputs() in OCEAN
    Throughout this manual are examples of nets and instances preceded by a
    "/" as well as
    examples without the "/". There is a significant difference between
    the two.
    If you create a design in the Cadence® analog design environment and
    save the OCEAN file,
    all net and instance names will be preceded with a "/", indicating
    they are schematic names.
    The netlist/amap directory must be available to map these schematic
    names to names
    the simulator understands. (If your design command points to the raw
    netlist in the netlist
    directory, the amap directory is there.)
    OCEAN Reference
    Introduction to OCEAN
    If you create a design or an OCEAN script by hand, or move the raw
    netlist from the netlist
    directory, the net and instance names might not be preceded with
    "/". This indicates that
    simulator names are used, and mapping is not necessary.
    If you are unsure whether schematic names or simulator names are used,
    after
    selectResult( S_resultsName ), type outputs() to see the list of net
    and instance
    names.
    Note: Although you can move the raw netlist file from the netlist
    directory, it is not advised.
    There are other files in the netlist directory that are now required to
    run OCEAN.
     
    Mr . SJ, Jan 25, 2005
    #3
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