spectre netlist format

Discussion in 'Cadence' started by HR, Oct 13, 2009.

  1. HR

    HR Guest

    Hi
    Can any one help me how can i defined the array of the variable in the
    spectre netlist
    Example;
    var[0:9] is my verilig AMS varibale
    In the spectre netlist how can i defined the above variable.
     
    HR, Oct 13, 2009
    #1
  2. HR wrote, on 10/13/09 15:56:
    I've no idea what you're asking here, even compensating for the typos. I don't
    know what relevance an Verilog AMS variable has in a spectre netlist.

    Please explain in more detail what you're trying to do!

    Regards,

    Andrew.
     
    Andrew Beckett, Oct 14, 2009
    #2
  3. HR

    Riad KACED Guest

    Hi HR,

    I'm struggling to undetsrand too ...
    Anyway, best way for you is to generate a Spectre Direct (Not AMS with
    spectre solver) netlist from your schematic to see how arrays (busses)
    are translated into Spectre.
    Starting from IC5.1.41.500.6.130, arrays 10-vector wire like Var<0:9>
    (as in Schematic notation) would be translated to Spectre as Var
    \<0\>, Var\<1\> ... etc. Prior to that version, it would have been
    translated as Var_0, Var_1 ... etc.

    Cheers,
    Riad.
     
    Riad KACED, Oct 15, 2009
    #3
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.