spectre model files

Hi -
I am trying to use spectre built-in primitives in my verilog AMS
design using Cadence Environment tools. From cdsdoc, I understand that
I have to create a primitive table in the directory in which I have my
design. And apart from the primitive table, I should also have a model
file. I am able to locate the main primitive table in
/cadence/ldv41/tools.sun4v/affirma_ams/etc/files/spec_builtin.apt, but
I cant find the model files...There are some model files in
/cadence/local/models/spectre, but they are all NMOS or PMOS models. I
was looking for resitors, capacitors, etc. Is there a specific
directory where I can find these models?
In the Spectre Simulator Circuit Reference, Component Statements
2 section, I do see the descriptions for 'physical resistor'...so does
it mean that I have to create my own model files for all these
components? But then, I have been using Spectre to simulate my
schematics, and I have never had to create model files for the
capacitors I used in those schematics...so there should be some place
where these models should be stored right...?

Vineet.

 

Vineet:
You should be able to use resistors and capacitors from analogLib
without specifying models. You could also use structural resistors or
capacitors in the verilogams code. Note if in the code they seem to
show up red in the HED.

If you use ldv51 you don't need an apt file.

You point to your spectre model files with the following in your
hdl.var:
DEFINE MODELPATH yourpath/yourmodel.scs

 

Hi Erik,
I do have analogLib and I am able to use it, but only in my schematic
view. If I instantiate a structural capacitor in my verilogams view
code I get this error
ncvlog: *E,ILLPRI (/home/student/vineet/assign/ams_work/CEA/cea_main/verilogams/verilog.vams,20|12):
illegal expression primary [4.2(IEEE)].
capacitor #(.c(10u)) Ce(node3, gnd);

I even tried to instantiate the capacitor from the ahdlLib, but that
also gives the same error.
ncvlog: *E,ILLPRI (/home/student/vineet/assign/ams_work/CEA/cea_main/verilogams/verilog.vams,16|7):
illegal expression primary [4.2(IEEE)].
cap #(.c(1u)) Cin(node5, node4);

All these libraries are there in my library path and I can see them in
my Library Manager, but I wonder why is it that I am not able to
instantiate them.

We have ldv41 here.

I did come across a model file 'spectre_prim.scs' and the associated
apt 'spectre_prim.scs.apt' in the SAR_A2D quick start tutorial thats
available to us. But this modelfile has only the pmos and nmos
models...
CDSDOC says that I can instantiate analog primitives just like any
other built-in primitive provided that I have the modelfile and the
associated apt file (generated using the genalgprim command) in the
working directory. I am starting to think that these particular .scs
modelfiles are the ones that are missing, and probably they are not
there in my lab. Could that be the problem...?

Vineet.

 

Vineet:
You shouldn't need models for generic caps and resistors. Place down
a few passive components from analogLib and look at the generated
verilog.vams netlist. The syntax should be similar to what you have.

Can you get ldv5.1?
---
Erik

 

Hi Erik,

I have already tried that. I used the code from the verilog.vams file
of the 'schematic' view in my 'verilogams' view and still the error
persisted.

capacitor #(.c(10u))
`ifdef INCA (* integer library_binding = "analogLib"; *) `endif
C3 ( cds_globals.\gnda! , net21 );

This is the error message I got.

ncvlog: 04.10-s023: (c) Copyright 1995-2004 Cadence Design Systems,
Inc.
capacitor #(.c(10u))
|
ncvlog: *E,MISEXX (/home/student/vineet/assign/ams_work/CEA/cea_main/verilogams/verilog.vams,16|11):
expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
capacitor #(.c(10u))
|
ncvlog: *E,ILLPRI (/home/student/vineet/assign/ams_work/CEA/cea_main/verilogams/verilog.vams,16|13):
illegal expression primary [4.2(IEEE)].
`ifdef INCA (* integer library_binding = "analogLib"; *) `endif
|
ncvlog: *E,ILLPRI (/home/student/vineet/assign/ams_work/CEA/cea_main/verilogams/verilog.vams,17|13):
illegal expression primary [4.2(IEEE)].
`ifdef INCA (* integer library_binding = "analogLib"; *) `endif

I tried similar step with the 'cap' from ahdlLib...but same result.
I even tried to parse from the unix prompt with "ncvlog -ams
verilog.vams" command, but still the error were the same.

Normally in Synopsys Design compiler to compile code with `ifdef
directive, we have to set certain variables. Is that the case with
cadence as well. But then that should come into consideration only at
the compile stage. I am getting stuck at the parsing stage itself !!

No, I dont think getting a new license is possible. Our school's
license was renewed just this Jan and thats when we got all this AMS
Environment stuff. And thats y no one here knows much about it. I
being a student am not even able to create a Sourcelink account...

I am pasting my hdl.var file here. Can you please see and let me know
if I have all the variables set or not

softinclude $AMSHOME/tools/inca/files/hdl.var
define cdslib ./cds.lib
#Define WORK amslib
Define NCVLOGOPTS -linedebug
#define ALGPRIMPATH /home/student/vineet/assign/SAR_A2D/spectre_prim.scs
#define MODELPATH /apps/cadence/ic50/tools.sun4v/dfII/etc/cdslib/artist/analogLib
#define MODELPATH /apps/cadence/ldv41/tools.sun4v/affirma_ams/etc/files/spec_builtin
define MODELPATH /apps/cadence/ldv41/tools/affirma_ams/etc/files/spec_builtin
define VIEW_MAP ($VIEW_MAP, .vs => shell)

And this is my ams.env...

amsDirect hdlVarFile string "/home/student/vineet/assign/ams_work/hdl.var"
amsDirect.vhdl amsEligibleViewTypes string "schematic"
amsDirect.vlog ifdefLanguageExtensions boolean t
amsDirect.vlog checkOnly boolean t
amsDirect.vlog includeFiles string "(disciplines.vams)(constants.vams)"
amsDirect.vlog checkAndNetlist boolean t

My cds.lib has this relevant line that should be required.
SOFTINCLUDE $AMSHOME/tools/inca/files/cds.lib
Here AMSHOME is set in my .profile as -
export AMSHOME=/apps/cadence/ldv41

I am really sorry for bothering you with so much. But I dont know why
there is hardly any stuff on google on AMS Designer, and moreover I
couldnt even find a single university that is using Cadence AMS
Designer AND has an online tutorial on it ! Your help is very much
appreciated.

regards,
Vineet.