some begginers problems

I've got an assignement to write a paper on some cadence tools, but I have
problem understanding basic terminology. What exactly are, and what is the
difference between NC-Verilog and Verilog XL?

Thanks,
Ivan.

 

NC Verilog is a much newer generation of Verilog simulator, compared with
Verilog-XL. The NC family of tools have a compile to native code approach,
followed by elaboration (rather like linking), and supported mixed language
(Verilog, VHDL, System C) simulator, as well as Mixed-signal simulation using
VHDL-AMS and Verilog-AMS in the AMS Designer tools.

Essentially both understand Verilog though - but the flavour of Verilog
supported by Verilog-XL is not the latest revision of the language.

Regards,

Andrew.