SoC Encounter

Discussion in 'Cadence' started by luc, May 14, 2004.

  1. luc

    luc Guest

    Hi,

    If you start with P&R (SoC Encounter) you have to read a verilog
    netlist.
    Most of the time this netlist doesn't contain any Power/Ground pads.
    How is it possible to create P/G + Corners in the IO-placement file
    and distribute the create cells around the chip.


    Many thanks

    luc
     
    luc, May 14, 2004
    #1
  2. luc

    Paul Muller Guest

    Hi Luc,

    before reading the IOC file, you must first read the verilog file, the a
    DEF file which contains all information about corner and PG cells.

    You can find the syntax in the SoCE documentation.

    Paul
     
    Paul Muller, May 14, 2004
    #2
  3. luc

    Paul Muller Guest

    Hi Luc,

    I must admit I did not go yet that far in the use of SoCE and I guessed
    it was the same than for SE. That's where my first explanation came
    from. But apparently it's not.

    I had a look at the documentation. Did you try to use the
    Power - Edit Pad Location menu? The power pad locations should be
    defined in a .pp file as described in the documentation in chapter 16,
    Running Power Analysis.

    Please give feed-back on this solution.

    Paul
     
    Paul Muller, May 14, 2004
    #3
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