Simulating VHDL in AMS

Is it possible to simulate digital VHDL in AMS? I simulate Verilog
among a analogic circuit without any problem. But, when I put a vhdl
file in the same place, the following errors appear.



SOFTINCLUDE ../../affirma_ams/etc/connect_lib/cds.lib
|
ncvlog: *W,DLCIML (/opt/cadence/IUS62/tools/inca/files/cds.lib,10):
cds.lib CDS.LIB file included multiple times '/mnt/debian/opt/cadence/
IUS62/tools.lnx86/affirma_ams/etc/connect_lib/cds.lib' (cds.lib
command ignored).
file: /home/usuarios/taimur/silicon/wkams/cont_vhdl/cds_globals/
counter_tb_config/verilog.vams
`include "disciplines.vams"
|
ncvlog: *E,COFILX (/home/usuarios/taimur/silicon/wkams/cont_vhdl/
cds_globals/counter_tb_config/verilog.vams,8|26): cannot open include
file '/opt/cadence/IC612/tools/spectre/etc/ahdl/disciplines.vams'.
electrical \gnd! ;
|
ncvlog: *E,EXPLPA (/home/usuarios/taimur/silicon/wkams/cont_vhdl/
cds_globals/counter_tb_config/verilog.vams,13|20): expecting a left
parenthesis ('(') [12.1.2][7.1(IEEE)].
module cont_vhdl.cds_globals:counter_tb_config
errors: 1, warnings: 0
Total errors/warnings found outside modules and primitives:
errors: 1, warnings: 1
Failed to compile ('cont_vhdl' 'cds_globals' 'counter_tb_config').
ncvhdl: 06.11-s005: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
SOFTINCLUDE ../../affirma_ams/etc/connect_lib/cds.lib
|
ncvhdl: *W,DLCIML (/opt/cadence/IUS62/tools/inca/files/cds.lib,10):
cds.lib CDS.LIB file included multiple times '/mnt/debian/opt/cadence/
IUS62/tools.lnx86/affirma_ams/etc/connect_lib/cds.lib' (cds.lib
command ignored).
SOFTINCLUDE ../../affirma_ams/etc/connect_lib/cds.lib
|
ncvhdl_p: *W,DLCIML (/opt/cadence/IUS62/tools/inca/files/cds.lib,10):
cds.lib CDS.LIB file included multiple times '/mnt/debian/opt/cadence/
IUS62/tools.lnx86/affirma_ams/etc/connect_lib/cds.lib' (cds.lib
command ignored).
/home/usuarios/taimur/silicon/wkams/cont_vhdl/counter/entity/vhdl.vhd:
ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /opt/cadence/IUS62/tools/
inca/files/STD.
Failed to compile ('cont_vhdl' 'counter' 'entity').
ncvhdl: 06.11-s005: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
SOFTINCLUDE ../../affirma_ams/etc/connect_lib/cds.lib
|
ncvhdl: *W,DLCIML (/opt/cadence/IUS62/tools/inca/files/cds.lib,10):
cds.lib CDS.LIB file included multiple times '/mnt/debian/opt/cadence/
IUS62/tools.lnx86/affirma_ams/etc/connect_lib/cds.lib' (cds.lib
command ignored).
SOFTINCLUDE ../../affirma_ams/etc/connect_lib/cds.lib
|
ncvhdl_p: *W,DLCIML (/opt/cadence/IUS62/tools/inca/files/cds.lib,10):
cds.lib CDS.LIB file included multiple times '/mnt/debian/opt/cadence/
IUS62/tools.lnx86/affirma_ams/etc/connect_lib/cds.lib' (cds.lib
command ignored).
/home/usuarios/taimur/silicon/wkams/cont_vhdl/counter/behavioral/
vhdl.vhd:
architecture behavioral of counter is
|
ncvhdl_p: *E,ENNOFN (/home/usuarios/taimur/silicon/wkams/cont_vhdl/
counter/behavioral/vhdl.vhd,5|33): Intermediate file for entity
'COUNTER' could not be loaded, entity may require re-analysis.
errors: 1, warnings: 0
ncvhdl_p: *W,SPUNFW: specific library unit was never processed
'counter:behavioral'.
Failed to compile ('cont_vhdl' 'counter' 'behavioral').
ncvlog: 06.11-s005: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
SOFTINCLUDE ../../affirma_ams/etc/connect_lib/cds.lib
|
ncvlog: *W,DLCIML (/opt/cadence/IUS62/tools/inca/files/cds.lib,10):
cds.lib CDS.LIB file included multiple times '/mnt/debian/opt/cadence/
IUS62/tools.lnx86/affirma_ams/etc/connect_lib/cds.lib' (cds.lib
command ignored).
file: /home/usuarios/taimur/silicon/wkams/cont_vhdl/counter_tb/
schematic/verilog.vams
`include "disciplines.vams"
|
ncvlog: *E,COFILX (/home/usuarios/taimur/silicon/wkams/cont_vhdl/
counter_tb/schematic/verilog.vams,4|26): cannot open include file '/
opt/cadence/IC612/tools/spectre/etc/ahdl/disciplines.vams'.
module cont_vhdl.counter_tb:schematic
errors: 0, warnings: 0
Total errors/warnings found outside modules and primitives:
errors: 1, warnings: 1
Failed to compile ('cont_vhdl' 'counter_tb' 'schematic').
Compilation failed.
Successfully compiled: 0
Failed to compile: 4


Can somebody help me? Is there one more step that I should do to
simulate vhdl through ams?

Thanks in advance.

 

Taimur wrote, on 06/26/08 22:16:

You have two separate problems. One is that it is getting confused when it tries
to find the "ncroot" (i.e. the root of the ncsim installation). This is because
you have <IC612instDir>/tools/bin/ncroot present. The reason this is present is
because you did NOT do the "configuration" step when IC612 was installed. The
configuration step will do various things, including compiling some libraries,
but importantly it removes the nc* links from tools/bin. The nc commands are in
the IC installation to support VHDL import now, which uses ncvhdl rather than
leapfrog.

The second problem is that the VHDL cannot compile because the VHDL libraries in
the IUS installation have not been compiled. This is also because (most likely)
the configuration step hasn't been performed on your IUS62 installation.

It is important to run the configuration step with many installations to finish
off the installation. That hasn't happened here, and that's why it is breaking.
Note that the same would be needed in order to run a straight digital VHDL
simulation, so it's not unique to AMS.

Regards,

Andrew.

 

Thank you, Andrew. In fact, I solved this problem setting the
environmental variable LVSHOME to the IUS path. But I didn't know that
it was some defects in my installation. I very apreciate your help.

 

Taimur wrote, on 06/28/08 18:09:

Hmm. I can't see how that would help! I presume LVSHOME must be something unique
to your environment - it's nothing to do with the Cadence tools.

Andrew.