Simulating Verilog-A model using spectre.

Discussion in 'Cadence' started by Gunnar Munder, Apr 29, 2005.

  1. Gunnar Munder

    Gunnar Munder Guest

    You have to add the Verilog-A view to the switch view list in your
    Analog Design Environment window under Setup->Environment Options. The
    view list has to look like that: "spectre cmos_sch schematic
    veriloga". Whatever view is found first - beginning from the left - is
    gonna be used. Having a schematic and a veriloga view in one cell you
    need to make sure the one you want to simulate is further left in the
    view list.

    Have fun
    Gunnar
     
    Gunnar Munder, Apr 29, 2005
    #1
  2. Gunnar Munder

    kamesh Guest

    Thanks Svenn and Gunnar.. it helped me..
     
    kamesh, May 2, 2005
    #2
  3. Gunnar Munder

    kvaddina Guest

    Thanks Svenn and Gunnar. It helped me solve this probelm.. Now I could
    simulate my model..
     
    kvaddina, May 2, 2005
    #3
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