Simulating Verilog-A model using spectre.

Discussion in 'Cadence' started by kvaddina, Apr 28, 2005.

  1. kvaddina

    kvaddina Guest

    Dear all,

    I am having a problem simulating Verilog-A model using spectre.

    I have added my Verilog-A symbol to my circuit(8-bit Adder) and now
    wanted to check whether the Verilog-A model does what it is suppossed
    to do. When I try to simulate it (Transient mode..) it gives me the
    following error.

    Running Artist Hierarchical Netlisting ...
    ERROR: Netlister: unable to descend into any of the views defined in
    the view list: "spectreS cmos_sch schematic" for instance I5 in cell
    Add_rpl_8.

    Either add one of these views to: Library:MyLib Cell:GlitchAnalyzer or
    modify the view list to contain an existing view.

    End netlisting Apr 28 18:59:57 2005

    "Netlister: There were errors, no netlist was produced."
    ...unsuccessful.
    ...unsuccessful.

    Can some one help me out. I am a Newbie to cadence.

    Thanks and Regards,
    kvaddina.
     
    kvaddina, Apr 28, 2005
    #1
  2. kvaddina

    Svenn Are Bjerkem Guest

    The magic lies in the view list: veriloga is not listed, and thus the
    netlister does not use your verilog-A model. You have to prepend your view
    list with veriloga.
    Depending on if you use a config or schematic view for simulation you extend
    the view list in the simulation window Setup->Environment ... or extend it
    in the hierarchy editor directly.

    I also recomend to read the anasimhelp.pdf in the
    $CDS_INST_DIR/doc/anasimhelp/ directory.
     
    Svenn Are Bjerkem, Apr 29, 2005
    #2
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