simulating 3rd party standard lib cells

Hi

I am a newbie to cadence. Well I am actually a designer and didn't
really care that much before how cadence worked - I should have.
Anyway, I need to simulate standard library compnents [artisan] and
can't work out how to link these to the artist simulator. All I know is
that I have cdl netlist for the standard lib and some symbol views. I
guess I need to link the views with correct port mapping info
for the simulator. I have tried converting netlists to spectre,
modifying cdf props etc. but to be honest I don't know what am am
really doing and the cadence doc is not helpful or at least I can't
find anything.

regards
Kev

 

You have to read in the cdl netlist to Cadence DFII
and create a standard cell library for DFII.
You might also do this with the GDSII for layout view.

CIW: "File -> Import -> CDL..."
As reference library you have to use your primitive device library,
you also might use a device mapping scheme.

<install_dir>/doc/transref/transref.pdf

Bernd

 

I am curious why you would like to take the effort to redo the work
that Artisan has already done. I thought it was Artisans business model
to provide their customers with already characterized libraries for
whatever technology.

If all you want to do is to have a look at the structures of the
libraries, there is a commercial tool called SpiceVision from Concept
Engineering which does a great job in recognizing structures in
netlists.

 

Sven,

Artisan provides some free Std. Cell libraries for various
si. foundries. Now because they are free, or what ever commercial
model the use in background with the foundry, they just provide the
libraries for the digital use model.

Now if you work in a mixed signal environment you either have to pay
Artisan to give you the data to use inside Cadence DFII or you have
to spend some effort to create the data your self.

I assume the second is what Kevin intent to want to do.

Bernd

 

If I would have to do a lot of netlist conversion work, I would really
recomend SpiceVision and its SKILL out functionality. The price of the
license is saved worktime. I have tried the import function of ic61 and
compared to SV it is lightyears behind.

 

Hi,

Yes. you are right it is for mixed signal environment. More
specifically it is
for an adc interface and the designer would like to use the standard
cells
and he needs to simulate with artist.

Aside, I believe it is better to create a full custom standard cell lib
and not a supplied version as I have seen issues when porting from one
tech to another.
But others would like to use the core standard libs it saves some
time....

And as far as I know artisan/arm don't provide the complete database
that we require,
if they do then it hasn't been installed properly and I am stuck with
getting to know
the ends and outs of cadence. ;-) !!

Kevin

 

Kevin, I have worked with the Artisan standard cells before, where
exactly are you having the issues?

In my case,as in the one you mention, they give you symbols, so the
messiest part is done. CDLin the spice to get usable (though certainly
not neat) schematics and you should have everything you need to get
going on simulation with spectre. Remember that the standard cells use
global power supplies (typically VDD! and VSS!) that you will have to
add sources for in order to get the sims to work.

There are several minor issues you may have to deal with if you want to
use them in the complete flow with AMS especially. Let me know if you
need more help...

David

 

Hi David,
The cdl I was given was not correct so i have to wait for that.
I had tried the cdlin with that netlist but didn't seems to work but
maybe
the netlist didn't match the symbols...
will let you know how i get on.
Kevin

 

Hi

I now final have a proper cdl netlist. However, when I try to cdlin
the netlsit all i get is a "mos" cell created.

I ahve also converted the netlist to spectre and am having problems
as I want to add inherited supplies to the stanard cell lib rather that
have
global VDD and VSS. I get it to netlist but it doen't work. [simple
inverter]

I changed to standard cell description fo an inverter from/to the
follwoing:

..subckt INVX1 Y A
M0 Y A VSS VSS NCH l=0.18u w=0.6u
M1 VDD A Y VDD PCH l=0.18u w=0.9u
..ends INVX1

to

simulator lang=spectre

subckt INVX1 Y A inh_vdd inh_vss
M0 ( Y A inh_vss inh_vss ) nch l=0.18u w=0.6u
M1 ( inh_vdd A Y inh_vdd ) pch l=0.18u w=0.9u
ends INVX1

However, it doesn't work so it seems that the inherited suppiles are
not being passed properly by the cdf. [componentName = INVX1 termOrder
"Y" "A" are the only 2 cdf params I set].

However if one draws a schmatci of such and inverter with inherited
supplies the componentName = subcircuit and not INVX1.

Any ideas?

Kevin

 

Kev, it sounds like you are not getting the correct primitives, which
usually means you are not telling cdlin where your PDK devides are when
you run cdlin.

 

I got a bit sidetracked here with cdlin - when in fact I am more
concerned on how to simulate a standard cell lib.

I can simualte if I convert the nodes VSS and VDD to VSS! and VDD! in
the netlist. but then that means that I ahev 2 global nodes i.e.e all
my stanard cell instances will be shorted through these nodes. Now I
want to be able to replace these nodes by inherited connections but I
can seem to get the cdf paramters correct for netlisting....

Kevin

 

Kev,
to avoid this problem, I keep two copies of the cells, one with globals
and one with the power and ground pins added to them. I let the digital
tools use the ones with globals (because that is what they expect) and
I substitute in the ones with power pins when it comes back to me. It
is a bit of a hassle, but I find it works out well because I can always
tell where my cells are connected.

Yes, I have had issues in the past with globals and LVS....


David

 

That's exactly the problem that Inherited connections are intended to solve. By
using inherited connections, you can have pins or nets in your low level digital
standard cells which don't appear on the symbols - they default to global nets,
but can be overridden at some higher level in the hierarchy using netSet
properties.

In the resulting transistor level netlists, extra pins will be added to
subcircuits to pass the power supplies. Verilog netlists however would not go
down as far as the transistor level circuits, and so would not see the net
expressions, and consequently not need to add the additional power pins - which
would line up with usual digital usage of not having to connect up power
supplies.

There's a good inherited connections tutorial on sourcelink (see previous
postings from my esteemed colleague John Gianni on this), so I suggest taking a
look at that.

Regards,

Andrew.

 

What (built-in) tools would you recomend when rearranging the inherited
nets when, let's say, power pins are added or removed? Is there a way
to create a tree-view of how cells are attached to the various
inherited nets? Currently interesting is IC5.1 but sooner or later
everybody run >IC6.*

We use inherited nets a lot and I think the concept is working good. I
find that there is a huge lack in supporting tools for rearranging.