Silicon Ensemble then Manual Layout

Discussion in 'Cadence' started by jools, Sep 10, 2003.

  1. jools

    jools Guest

    Ive a design which I can automatically layout and route (via a script) in
    silicon ensemble, which is very useful. However this tool doesnt let me
    manipulate the result afterwards.

    Can I adopt a design flow somehow using silicon ensemble to layout and route
    the design, and afterwards manipulate it as I wish, ie move cells etc.

    As we need to layout, to balance the power; but to layout and route it by
    hand would be far to time consuming and error prone.

    thanks

    jools
     
    jools, Sep 10, 2003
    #1
  2. Hi,

    You can export DEF file from SE, import it into Cadence dfII, than
    use Virtuoso to do the modifications.

    Note that this may by time consuming - after each ECO you will have
    to redo all the manual modifications.

    Robert
     
    Robert Szczygiel, Sep 11, 2003
    #2
  3. I have several customers using my Strategy product to import DEF,
    manipulate the layout using my layout editor, then re-exporting
    out the design as DEF or gds2. Because one of the editor design
    objectives was editing P&R data, there are many features (such
    as std cell row snap on a move) in the editor to help you edit
    this kind of data. Take a look at
    http://www.stabie-soft.com/strategy.html if you want more information.

    Mike
     
    Mike Stabenfeldt, Sep 11, 2003
    #3
  4. jools

    gregg kodra Guest

    jools

    you have a couple of options depending on your circumstances. the two points
    to consider ease of use and budget. to make manual manipulations with SE is
    a time consuming and error prone task. SE is really best used as a
    floorplanner and router. manual manipulations after a route are best done
    with a layout editor. there are several to choose from. they are all much
    easier to use then SE. i have used cadence, mentor, and stabie-soft. they
    all get the job done. if you already have one try it. if you don't, try
    and price them, they are all substancially cheaper then SE. and you may have
    to get one anyways because SE does not put the cell/macro gds in the gds it
    generates, so you have to merge to get final gds. do look at then def in
    interface on the layout editors. it allows you to keep the net information
    out of SE.
    lastly, you might want to consider altering your flow a little. from what you
    said you are altering power after the final route. you might want to consider
    having the router do the placement and power straping. then do your edits to
    the power routing, in SE or one of the layout editors (only done this with
    stabie-soft). the do the clock routing. then do the detail signal routing.

    hope this helps

    gregg kodra
     
    gregg kodra, Sep 12, 2003
    #4
  5. jools

    John Gianni Guest

    you have a couple of options depending on your circumstances. the two points
    1. I'm not sure the actual shipping date, but my custom IC flow engineering
    team has been testing the new Cadence 'Virtuoso Chip Editor' flow with the
    Cadence place and route tools (mostly SOC Encounter) since late January.

    We started with VCE versions 3.0 and 3.1 earlier this year, going only
    one way from the P&R world to the layout-editor world; and are currently
    testing the two-way flow builds of version 3.3 (which ship later in
    the year), all on the OpenAccess database (using as little LEF & DEF
    & GDSII as humanly possible, except as necessary workarounds to temporary
    bugs or not-yet-completed functionality in the tool-to-tool flow).

    2. Basically, we're integrating multiple separate RF, Analog, Memory,
    Mixed-Signal, & large/fast Digital IP using the Virtuoso Chip Editor
    (typically with the top-level floorplanned with Virtuoso Preview and
    routed with the Cadence Chip Assembly Router). (My philosophy is to
    test software the way the Customers is intended to use it.)

    Our first internal 'tapeout' milestone for a large communications chip
    (dual Leon processors, VGA, USB2, EIDE, Serial, Parallel, MACs, etc. with
    multiple 10/100 ethernet phys, a few additional PLLs from the custom flow,
    etc.) was July 25th of this year and which is being demoed Wednesday
    September 17th. at the International Cadence User Group conference:
    http://www.cadenceusers.org

    The digital blocks came from the Place & Route world (Artisan std. cells).
    The RF, Analog, & Mixed-Signal blocks came from the custom IC world.
    The memories typically came (for now) from Artisan memory compilers.

    3. It all ties together with the Virtuoso Chip Editor.

    Check out the demo at the ICU this week; or talk to your local sales
    team for more details and shipping dates.
     
    John Gianni, Sep 14, 2003
    #5
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